sys-kernel/linux-{image,sources}-redcore-lts-legacy : make sure we actually revert 52918ed5fcf05d97d257f4131e19479da18f5d16 upstream commit, not double apply it

1 files changed, 48 insertions, 79 deletions

diff --git a/sys-kernel/linux-image-redcore-lts-legacy/files/4.19-revert_52918ed5fcf05d97d257f4131e19479da18f5d16.patch b/sys-kernel/linux-image-redcore-lts-legacy/files/4.19-revert_52918ed5fcf05d97d257f4131e19479da18f5d16.patch
index d64d8efb..a19726f3 100644
--- a/sys-kernel/linux-image-redcore-lts-legacy/files/4.19-revert_52918ed5fcf05d97d257f4131e19479da18f5d16.patch
+++ b/sys-kernel/linux-image-redcore-lts-legacy/files/4.19-revert_52918ed5fcf05d97d257f4131e19479da18f5d16.patch
@@ -1,91 +1,60 @@
-From a4e761c9f63ae12c5e2fc586b77082fd07e54212 Mon Sep 17 00:00:00 2001
-From: Tom Lendacky <thomas.lendacky@amd.com>
-Date: Thu, 9 Jan 2020 17:42:16 -0600
-Subject: KVM: SVM: Override default MMIO mask if memory encryption is enabled
-
-commit 52918ed5fcf05d97d257f4131e19479da18f5d16 upstream.
-
-The KVM MMIO support uses bit 51 as the reserved bit to cause nested page
-faults when a guest performs MMIO. The AMD memory encryption support uses
-a CPUID function to define the encryption bit position. Given this, it is
-possible that these bits can conflict.
-
-Use svm_hardware_setup() to override the MMIO mask if memory encryption
-support is enabled. Various checks are performed to ensure that the mask
-is properly defined and rsvd_bits() is used to generate the new mask (as
-was done prior to the change that necessitated this patch).
-
-Fixes: 28a1f3ac1d0c ("kvm: x86: Set highest physical address bits in non-present/reserved SPTEs")
-Suggested-by: Sean Christopherson <sean.j.christopherson@intel.com>
-Reviewed-by: Sean Christopherson <sean.j.christopherson@intel.com>
-Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
-Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/kvm/svm.c | 43 +++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 43 insertions(+)
-
-diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
-index 0219693bf08e..3f0565e1a7a8 100644
---- a/arch/x86/kvm/svm.c
-+++ b/arch/x86/kvm/svm.c
-@@ -1298,6 +1298,47 @@ static void shrink_ple_window(struct kvm_vcpu *vcpu)
+diff -Nur a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
+--- a/arch/x86/kvm/svm.c	2020-03-05 15:42:23.000000000 +0000
++++ b/arch/x86/kvm/svm.c	2020-03-09 23:13:11.593860862 +0000
+@@ -1298,47 +1298,6 @@
  				    control->pause_filter_count, old);
  }
  
-+/*
-+ * The default MMIO mask is a single bit (excluding the present bit),
-+ * which could conflict with the memory encryption bit. Check for
-+ * memory encryption support and override the default MMIO mask if
-+ * memory encryption is enabled.
-+ */
-+static __init void svm_adjust_mmio_mask(void)
-+{
-+	unsigned int enc_bit, mask_bit;
-+	u64 msr, mask;
-+
-+	/* If there is no memory encryption support, use existing mask */
-+	if (cpuid_eax(0x80000000) < 0x8000001f)
-+		return;
-+
-+	/* If memory encryption is not enabled, use existing mask */
-+	rdmsrl(MSR_K8_SYSCFG, msr);
-+	if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
-+		return;
-+
-+	enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
-+	mask_bit = boot_cpu_data.x86_phys_bits;
-+
-+	/* Increment the mask bit if it is the same as the encryption bit */
-+	if (enc_bit == mask_bit)
-+		mask_bit++;
-+
-+	/*
-+	 * If the mask bit location is below 52, then some bits above the
-+	 * physical addressing limit will always be reserved, so use the
-+	 * rsvd_bits() function to generate the mask. This mask, along with
-+	 * the present bit, will be used to generate a page fault with
-+	 * PFER.RSV = 1.
-+	 *
-+	 * If the mask bit location is 52 (or above), then clear the mask.
-+	 */
-+	mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
-+
-+	kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
-+}
-+
+-/*
+- * The default MMIO mask is a single bit (excluding the present bit),
+- * which could conflict with the memory encryption bit. Check for
+- * memory encryption support and override the default MMIO mask if
+- * memory encryption is enabled.
+- */
+-static __init void svm_adjust_mmio_mask(void)
+-{
+-	unsigned int enc_bit, mask_bit;
+-	u64 msr, mask;
+-
+-	/* If there is no memory encryption support, use existing mask */
+-	if (cpuid_eax(0x80000000) < 0x8000001f)
+-		return;
+-
+-	/* If memory encryption is not enabled, use existing mask */
+-	rdmsrl(MSR_K8_SYSCFG, msr);
+-	if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
+-		return;
+-
+-	enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
+-	mask_bit = boot_cpu_data.x86_phys_bits;
+-
+-	/* Increment the mask bit if it is the same as the encryption bit */
+-	if (enc_bit == mask_bit)
+-		mask_bit++;
+-
+-	/*
+-	 * If the mask bit location is below 52, then some bits above the
+-	 * physical addressing limit will always be reserved, so use the
+-	 * rsvd_bits() function to generate the mask. This mask, along with
+-	 * the present bit, will be used to generate a page fault with
+-	 * PFER.RSV = 1.
+-	 *
+-	 * If the mask bit location is 52 (or above), then clear the mask.
+-	 */
+-	mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
+-
+-	kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
+-}
+-
  static __init int svm_hardware_setup(void)
  {
  	int cpu;
-@@ -1352,6 +1393,8 @@ static __init int svm_hardware_setup(void)
+@@ -1393,8 +1352,6 @@
  		}
  	}
  
-+	svm_adjust_mmio_mask();
-+
+-	svm_adjust_mmio_mask();
+-
  	for_each_possible_cpu(cpu) {
  		r = svm_cpu_init(cpu);
  		if (r)
--- 
-cgit 1.2-0.3.lf.el7
-