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authorV3n3RiX <venerix@koprulu.sector>2022-06-29 12:04:12 +0100
committerV3n3RiX <venerix@koprulu.sector>2022-06-29 12:04:12 +0100
commit0f558761aa2dee1017b4751e4017205e015a9560 (patch)
tree037df795519468a25d9362b4e95cdaeb84eb1cf9 /metadata/md5-cache/sci-electronics/iverilog-10.3
parent752d6256e5204b958b0ef7905675a940b5e9172f (diff)
gentoo resync : 29.12.2022
Diffstat (limited to 'metadata/md5-cache/sci-electronics/iverilog-10.3')
-rw-r--r--metadata/md5-cache/sci-electronics/iverilog-10.33
1 files changed, 2 insertions, 1 deletions
diff --git a/metadata/md5-cache/sci-electronics/iverilog-10.3 b/metadata/md5-cache/sci-electronics/iverilog-10.3
index b5b643467101..1b7e5043d30a 100644
--- a/metadata/md5-cache/sci-electronics/iverilog-10.3
+++ b/metadata/md5-cache/sci-electronics/iverilog-10.3
@@ -4,11 +4,12 @@ DEPEND=sys-libs/readline:= sys-libs/zlib
DESCRIPTION=A Verilog simulation and synthesis tool
EAPI=8
HOMEPAGE=http://iverilog.icarus.com https://github.com/steveicarus/iverilog
+INHERIT=autotools
IUSE=examples
KEYWORDS=~alpha amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 sparc x86
LICENSE=LGPL-2.1
RDEPEND=sys-libs/readline:= sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz -> iverilog-10.3.tar.gz
-_eclasses_=autotools b46e8992a8126c894fbdc8084fc040c4 gnuconfig b6b3e92f8b8c996400074b5f61a59256 libtool 241a8f577b9781a42a7421e53448a44e multilib 4a33c9008e5ee30cb8840a3fdc24df2b toolchain-funcs badd6e329e1f3e6bee99b35bf8763ce8
+_eclasses_=autotools 136117fb43a9bf5598530e9cc642f710 gnuconfig b6b3e92f8b8c996400074b5f61a59256 libtool 241a8f577b9781a42a7421e53448a44e multilib 4fbbbc98f236f1b43acd99476bc3cd85 toolchain-funcs e9da88162e7a3c60376e80c2c2adcdfb
_md5_=58efbb2a01446befd12dac822b0fcdea