diff options
author | V3n3RiX <venerix@koprulu.sector> | 2024-08-28 12:00:19 +0100 |
---|---|---|
committer | V3n3RiX <venerix@koprulu.sector> | 2024-08-28 12:00:19 +0100 |
commit | 7166f3a0a0b7886d340010458d0b130013cb9989 (patch) | |
tree | 3ff502007dde9dba943a004a3bf201ae4e0787bd /net-libs/nodejs | |
parent | 345c02ca33341652116ddec6705530223af2de85 (diff) |
gentoo auto-resync : 28:08:2024 - 12:00:19
Diffstat (limited to 'net-libs/nodejs')
-rw-r--r-- | net-libs/nodejs/Manifest | 1 | ||||
-rw-r--r-- | net-libs/nodejs/files/nodejs-20.11.0-riscv.patch | 155 |
2 files changed, 0 insertions, 156 deletions
diff --git a/net-libs/nodejs/Manifest b/net-libs/nodejs/Manifest index 039cd37f195e..39d9fd8463c8 100644 --- a/net-libs/nodejs/Manifest +++ b/net-libs/nodejs/Manifest @@ -1,5 +1,4 @@ AUX nodejs-18.16.0-paxmarking.patch 3470 BLAKE2B 4de01a4b3267d24c7c899a9caf8dae3975a8ed4a82cfe4df2ffc6858a3e1153bd6801ec5f5dc17ab5984ffa2d3b5ec9651c80e6993bd20c14865b0d873f58547 SHA512 5f49c1ca953421b3aa07e0b93375e99c9e5f543b48df3cff833f5e55f7e1b511971c56ed250e36c8a7465229db135a8d2bd1319f2d09368788f6152f06ced4f9 -AUX nodejs-20.11.0-riscv.patch 7660 BLAKE2B 8af657b4c87f892a7e8ab4e0b0f6c8927841585cf71971cb3a0e9b508c182222ace7178fd76f12000432df8a1b51c1a553616a3797a16b35f9499edce1e84638 SHA512 29b42307e017de0ef54c2e80e5e56d771a04f282ca858bcd3300c68ef4d72bb2fb5f2841a85a9845ee17f1909a33a64c798da9ed624feb34fcb11661dbe9fe69 AUX nodejs-20.6.0-paxmarking.patch 3143 BLAKE2B 34b93f63481177f1b70d26bdbdb27674533016dd5cefe4161cfa49c3defc6316cbbf22df024d28e9d42687be78fb0a6ce6e95334cad386d6371ff1f7fd9063ee SHA512 6604a1c8041e28bea0ea8c4dd168d44fb4ae7d25b15db4e20c220bcf3697d08de5205dde502dda4d061ace36e3f8f3511f646b00acc0382c2c8dff64cf1bf8b8 AUX nodejs-22.2.0-riscv.patch 1760 BLAKE2B f5f033dd589637481d2a2f3e67cdbb7a6052bdb187d2666b145a76f23da6e36adeddfe2b6e1718ae4412df914f8517bec2cdc5c15b18eb9dca5dad7a6668cc04 SHA512 f2ff6da8cf5dcc994a7a20342e2928dc1821fbbf42891009a6234b6051277e0200d7e3fbba63b9a2773887591d0ad5ceb1bb3d25e5efeb557f6d00109a80253c DIST node-v18.20.4.tar.xz 40445740 BLAKE2B 0675f2aba1d9a9cd9aeb665ecb3a0f61b9caf39daeb6154941f84b9c423caa7a658c14b8c2c5e12d94424b2470748ec7fad28ecb10390d37f92eb7e50f8adc26 SHA512 1ccef99ebee3906f5bad3c1582f9551ced9bed15e6a047d59d1a23c6110004fb46ea4bebcf9899748c64109f78788d7365ee956444e645eaf397dabbcddda21e diff --git a/net-libs/nodejs/files/nodejs-20.11.0-riscv.patch b/net-libs/nodejs/files/nodejs-20.11.0-riscv.patch deleted file mode 100644 index 3bf7a80ea078..000000000000 --- a/net-libs/nodejs/files/nodejs-20.11.0-riscv.patch +++ /dev/null @@ -1,155 +0,0 @@ -From dda5cdb15cfe5c7437f471054f5bd79a82b6eda2 Mon Sep 17 00:00:00 2001 -From: kxxt <rsworktech@outlook.com> -Date: Wed, 17 Jan 2024 09:16:34 +0800 -Subject: [PATCH] Revert "deps: V8: cherry-pick 13192d6e10fa" - -This reverts commit bc2ebb972b34f54e042de9636e7451d2526436a9, which -shouldn't be applied to v20.x. - -Fix https://github.com/nodejs/unofficial-builds/issues/106 ---- - common.gypi | 2 +- - deps/v8/src/builtins/riscv/builtins-riscv.cc | 2 +- - deps/v8/src/codegen/riscv/assembler-riscv-inl.h | 16 ++++++++-------- - deps/v8/src/codegen/riscv/assembler-riscv.h | 2 +- - deps/v8/src/execution/riscv/simulator-riscv.cc | 8 ++++---- - .../regexp/riscv/regexp-macro-assembler-riscv.cc | 2 +- - 6 files changed, 16 insertions(+), 16 deletions(-) - -diff --git a/common.gypi b/common.gypi -index db09a8a33df06..fa0729ffe45e8 100644 ---- a/common.gypi -+++ b/common.gypi -@@ -36,7 +36,7 @@ - - # Reset this number to 0 on major V8 upgrades. - # Increment by one for each non-official patch applied to deps/v8. -- 'v8_embedder_string': '-node.17', -+ 'v8_embedder_string': '-node.18', - - ##### V8 defaults for Node.js ##### - -diff --git a/deps/v8/src/builtins/riscv/builtins-riscv.cc b/deps/v8/src/builtins/riscv/builtins-riscv.cc -index d6091434b9b0a..3404562785991 100644 ---- a/deps/v8/src/builtins/riscv/builtins-riscv.cc -+++ b/deps/v8/src/builtins/riscv/builtins-riscv.cc -@@ -1512,7 +1512,7 @@ static void Generate_InterpreterEnterBytecode(MacroAssembler* masm) { - // Set the return address to the correct point in the interpreter entry - // trampoline. - Label builtin_trampoline, trampoline_loaded; -- Tagged<Smi> interpreter_entry_return_pc_offset( -+ Smi interpreter_entry_return_pc_offset( - masm->isolate()->heap()->interpreter_entry_return_pc_offset()); - DCHECK_NE(interpreter_entry_return_pc_offset, Smi::zero()); - -diff --git a/deps/v8/src/codegen/riscv/assembler-riscv-inl.h b/deps/v8/src/codegen/riscv/assembler-riscv-inl.h -index ca6d641e2c94e..55f191e6afe76 100644 ---- a/deps/v8/src/codegen/riscv/assembler-riscv-inl.h -+++ b/deps/v8/src/codegen/riscv/assembler-riscv-inl.h -@@ -128,9 +128,9 @@ Handle<HeapObject> Assembler::compressed_embedded_object_handle_at( - } - - void Assembler::deserialization_set_special_target_at( -- Address instruction_payload, Tagged<Code> code, Address target) { -+ Address instruction_payload, Code code, Address target) { - set_target_address_at(instruction_payload, -- !code.is_null() ? code->constant_pool() : kNullAddress, -+ !code.is_null() ? code.constant_pool() : kNullAddress, - target); - } - -@@ -159,13 +159,12 @@ void Assembler::deserialization_set_target_internal_reference_at( - } - } - --Tagged<HeapObject> RelocInfo::target_object(PtrComprCageBase cage_base) { -+HeapObject RelocInfo::target_object(PtrComprCageBase cage_base) { - DCHECK(IsCodeTarget(rmode_) || IsEmbeddedObjectMode(rmode_)); - if (IsCompressedEmbeddedObject(rmode_)) { -- return HeapObject::cast( -- Tagged<Object>(V8HeapCompressionScheme::DecompressTagged( -- cage_base, -- Assembler::target_compressed_address_at(pc_, constant_pool_)))); -+ return HeapObject::cast(Object(V8HeapCompressionScheme::DecompressTagged( -+ cage_base, -+ Assembler::target_compressed_address_at(pc_, constant_pool_)))); - } else { - return HeapObject::cast( - Object(Assembler::target_address_at(pc_, constant_pool_))); -@@ -187,7 +186,8 @@ Handle<HeapObject> RelocInfo::target_object_handle(Assembler* origin) { - } - } - --void RelocInfo::set_target_object(Tagged<HeapObject> target, -+void RelocInfo::set_target_object(Heap* heap, HeapObject target, -+ WriteBarrierMode write_barrier_mode, - ICacheFlushMode icache_flush_mode) { - DCHECK(IsCodeTarget(rmode_) || IsEmbeddedObjectMode(rmode_)); - if (IsCompressedEmbeddedObject(rmode_)) { -diff --git a/deps/v8/src/codegen/riscv/assembler-riscv.h b/deps/v8/src/codegen/riscv/assembler-riscv.h -index bcd5a62d324ee..ed222b52d6927 100644 ---- a/deps/v8/src/codegen/riscv/assembler-riscv.h -+++ b/deps/v8/src/codegen/riscv/assembler-riscv.h -@@ -286,7 +286,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase, - // This is for calls and branches within generated code. The serializer - // has already deserialized the lui/ori instructions etc. - inline static void deserialization_set_special_target_at(Address location, -- Tagged<Code> code, -+ Code code, - Address target); - - // Get the size of the special target encoded at 'instruction_payload'. -diff --git a/deps/v8/src/execution/riscv/simulator-riscv.cc b/deps/v8/src/execution/riscv/simulator-riscv.cc -index 052a2d67dd7e4..9582db489638a 100644 ---- a/deps/v8/src/execution/riscv/simulator-riscv.cc -+++ b/deps/v8/src/execution/riscv/simulator-riscv.cc -@@ -1781,7 +1781,7 @@ void RiscvDebugger::Debug() { - sreg_t value; - StdoutStream os; - if (GetValue(arg1, &value)) { -- Tagged<Object> obj(value); -+ Object obj(value); - os << arg1 << ": \n"; - #ifdef DEBUG - obj.Print(os); -@@ -1830,7 +1830,7 @@ void RiscvDebugger::Debug() { - PrintF(" 0x%012" PRIxPTR " : 0x%016" REGIx_FORMAT - " %14" REGId_FORMAT " ", - reinterpret_cast<intptr_t>(cur), *cur, *cur); -- Tagged<Object> obj(*cur); -+ Object obj(*cur); - Heap* current_heap = sim_->isolate_->heap(); - if (obj.IsSmi() || - IsValidHeapObject(current_heap, HeapObject::cast(obj))) { -@@ -4692,7 +4692,7 @@ bool Simulator::DecodeRvvVS() { - Builtin Simulator::LookUp(Address pc) { - for (Builtin builtin = Builtins::kFirst; builtin <= Builtins::kLast; - ++builtin) { -- if (builtins_.code(builtin)->contains(isolate_, pc)) return builtin; -+ if (builtins_.code(builtin).contains(isolate_, pc)) return builtin; - } - return Builtin::kNoBuiltinId; - } -@@ -4709,7 +4709,7 @@ void Simulator::DecodeRVIType() { - if (builtin != Builtin::kNoBuiltinId) { - auto code = builtins_.code(builtin); - if ((rs1_reg() != ra || imm12() != 0)) { -- if ((Address)get_pc() == code->instruction_start()) { -+ if ((Address)get_pc() == code.InstructionStart()) { - sreg_t arg0 = get_register(a0); - sreg_t arg1 = get_register(a1); - sreg_t arg2 = get_register(a2); -diff --git a/deps/v8/src/regexp/riscv/regexp-macro-assembler-riscv.cc b/deps/v8/src/regexp/riscv/regexp-macro-assembler-riscv.cc -index 72f89767eb348..4063b4b3d2194 100644 ---- a/deps/v8/src/regexp/riscv/regexp-macro-assembler-riscv.cc -+++ b/deps/v8/src/regexp/riscv/regexp-macro-assembler-riscv.cc -@@ -1211,7 +1211,7 @@ static T* frame_entry_address(Address re_frame, int frame_offset) { - int64_t RegExpMacroAssemblerRISCV::CheckStackGuardState(Address* return_address, - Address raw_code, - Address re_frame) { -- Tagged<InstructionStream> re_code = InstructionStream::cast(Object(raw_code)); -+ InstructionStream re_code = InstructionStream::cast(Object(raw_code)); - return NativeRegExpMacroAssembler::CheckStackGuardState( - frame_entry<Isolate*>(re_frame, kIsolateOffset), - static_cast<int>(frame_entry<int64_t>(re_frame, kStartIndexOffset)), - |