gentoo resync : 15.01.2020

4 files changed, 161 insertions, 11 deletions

diff --git a/sci-electronics/iverilog/Manifest b/sci-electronics/iverilog/Manifest
index bbfe636b6d2b..3d756b0719da 100644
--- a/sci-electronics/iverilog/Manifest
+++ b/sci-electronics/iverilog/Manifest
@@ -1,7 +1,10 @@
+DIST iverilog-10.3.tar.gz 1600835 BLAKE2B 107c57c61fb27c18f4020f7853bf6ca83d1a86fdc73c57ea207828baf6b7a26d42e43ce7b33580f050a4c0b8f63bca6accecf678323a3bbbee1eb9c1d8fa2caa SHA512 67076e19a208576c21a0462ff7d15d00a9d47740c47518a5523bd928b3118360d85eb84c317963717d15e5246ece3727259f6ff3baf59e195340530cc9086a1d
 DIST verilog-0.9.6.tar.gz 1219982 BLAKE2B 12f7dfb1ab8b7e4524cf0a3061ce801bfa741015fc1446aef7ffe51c42d76b5d0578e78ce13cd8c3fb6bac580e9da1ed11ca03e1fd02f8cb75dd74425546f851 SHA512 63c18f211eb9711547db65b859551063129cf18acb1196eaa88562f194231079fe929a6f7b8fbe2160863c521f02dde079e792f1b0bbe1c2514deafd55d5288c
 DIST verilog-0.9.7.tar.gz 1238088 BLAKE2B c0b173b4857abc0d35ad05d9f11d5265763c92e625aadb1b487978c40e0679725b8e6de0fc05cc8e4bc7a6db6e1d9abacf886942b05e27d8513b9586cca156f9 SHA512 1a81f132c667f5cd33a11156364a366806ef9b6ef59b86f69df852af79cc92db17df8db0bace4e3c14929b0110df0aa7d83f35f664057e715842acf7bd21c1f5
 DIST verilog-10.2.tar.gz 1695227 BLAKE2B ea2488de55ef60a248e7f5ffd5e06c6d86d57f3cff4536cb64a727ab70d8868847e53beec093e21243a1e81ede021b0ccde771d66ce1d986f737b5d925aaff11 SHA512 21e0861ee994daf0a98d0da3e0ad665e37cba4669faa873ae57d05eb41794b6cc2948c88cc07ebe1e9266850ad2bad189096ae6911b9c4064f772279d0901aef
 EBUILD iverilog-0.9.6.ebuild 1123 BLAKE2B bd804cd0e062aad50ae3d13b86181431634a9ffc5e06f725bd3c3dba8e3cdcdcefe970ac5c5af9dd12bdcf6e6efe45158d8e262c445f155b51bc7289e8f84782 SHA512 b5bfe49d06522810054db72693e30220ceda8e0e1886a45a2094024b6e114cb3c8e943c333308fd0f17facdaa5bf7066aedc33120bed3fbb942ff0320733695a
 EBUILD iverilog-0.9.7.ebuild 1127 BLAKE2B 0df427e1b40eb81301e3ad5a783ba439d11e29f64bba8db1bae0b814807525367a1009b7dd3daad2c04e315c0899b32e6b83fa5c034dc821350151e234546616 SHA512 0166372b9aec56da2edce510783bdd9aece5610f418d0ceea081a72f0b7277b62133fcd866360fea449395a7e9bd6a7f24ae03c2373184bd14c1c951e81d4e33
 EBUILD iverilog-10.2.ebuild 645 BLAKE2B bfa32a5577961ef503b53654f1c076cfe8a1cb000a2986ca603404115502332f6c8be2ca10b925ce70f148ee394bed96c6e4f19c303664cde249de7e9dd8bc43 SHA512 de3c3cb13a45900e02cc90a9283a41f5d32e5a6fb6c9f8e261bd356fbcfafd98fd65e38c42324d246927360a6b1af17c0b9d110b38d6f2ce19921b350a19f905
-MISC metadata.xml 611 BLAKE2B 6399e25c12a2b7ee9fc9f047361b4d8d34b785507ba3e0ee5e42b8fb13763c37570e4fc01723fd60fd7ebbef0441a852e96bd44c385a4cab73b1a50130dbbc40 SHA512 83a276b3b5dcb6dff9a03fe2886ad4476833e4a375af2e5c1b1a597a6a16374f843e319bf03283aabe2c7e12e4d5fa0a6125963177c6227e83bdc8dbae7cbd0a
+EBUILD iverilog-10.3.ebuild 1723 BLAKE2B f0b8caf5e2790f18ede1445111cbaf7cbc9c5dd8f2d9e741fd4b42fe8aadb36f149633d83dcde6e133038065a38535b9fd2cd6dc1b6ccd8c2fc5b6867e4aead6 SHA512 50b62bb39bdbd4d146b6cf71326548a9181b35c0de4091cac420e6a63753053880eeed91a6a021610f245fe2ab46f25481f18748c6239dd78322de0cf02aa930
+EBUILD iverilog-9999.ebuild 1723 BLAKE2B f0b8caf5e2790f18ede1445111cbaf7cbc9c5dd8f2d9e741fd4b42fe8aadb36f149633d83dcde6e133038065a38535b9fd2cd6dc1b6ccd8c2fc5b6867e4aead6 SHA512 50b62bb39bdbd4d146b6cf71326548a9181b35c0de4091cac420e6a63753053880eeed91a6a021610f245fe2ab46f25481f18748c6239dd78322de0cf02aa930
+MISC metadata.xml 904 BLAKE2B 92e78cfceee82ffb4feaee92810d496bf78c3321a81c97fbcc0038244e2ea58e87fec57254ebd90852a4d308bd08d944659ce59b339b2762ba26843c8ad59cb3 SHA512 8c3633d7bea101dc771c26355b40d309eb5b0b3ea7bbf3538faaa9c7098253eb623aac3f9e312aed25a9262116d013784adf02d9f2a3943a5fbec3733dab250f
diff --git a/sci-electronics/iverilog/iverilog-10.3.ebuild b/sci-electronics/iverilog/iverilog-10.3.ebuild
new file mode 100644
index 000000000000..183ed6f2023f
--- /dev/null
+++ b/sci-electronics/iverilog/iverilog-10.3.ebuild
@@ -0,0 +1,68 @@
+# Copyright 1999-2020 Gentoo Authors
+# Distributed under the terms of the GNU General Public License v2
+
+EAPI=7
+
+inherit autotools
+
+GITHUB_PV=$(ver_rs 1- '_')
+
+DESCRIPTION="A Verilog simulation and synthesis tool"
+HOMEPAGE="
+	http://iverilog.icarus.com
+	https://github.com/steveicarus/iverilog
+"
+
+if [[ ${PV} == "9999" ]] ; then
+	inherit git-r3
+	EGIT_REPO_URI="https://github.com/steveicarus/${PN}.git"
+else
+	SRC_URI="https://github.com/steveicarus/${PN}/archive/v${GITHUB_PV}.tar.gz -> ${P}.tar.gz"
+	KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sh ~sparc ~x86"
+	S="${WORKDIR}/${PN}-${GITHUB_PV}"
+fi
+
+LICENSE="LGPL-2.1"
+SLOT="0"
+IUSE="examples"
+
+# If you are building from git, you will also need gperf to generate
+# the configure scripts.
+RDEPEND="
+	sys-libs/readline:0
+	sys-libs/zlib
+"
+
+DEPEND="
+	dev-util/gperf
+	${RDEPEND}
+"
+
+src_prepare() {
+	default
+
+	# From upstreams autoconf.sh, to make it utilize the autotools eclass
+	# Here translate the autoconf.sh, equivalent to the following code
+	# > sh autoconf.sh
+
+	# Autoconf in root ...
+	eautoconf --force
+	# Precompiling lexor_keyword.gperf
+	gperf -o -i 7 -C -k 1-4,6,9,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc || die
+	# Precompiling vhdlpp/lexor_keyword.gperf
+	cd vhdlpp || die
+	gperf -o -i 7 --ignore-case -C -k 1-4,6,9,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc || die
+}
+
+src_install() {
+	local DOCS=( *.txt )
+	# Default build fails with parallel jobs,
+	# https://github.com/steveicarus/iverilog/pull/294
+	emake installdirs DESTDIR="${D}"
+	default
+
+	if use examples; then
+		dodoc -r examples
+		docompress -x /usr/share/doc/${PF}/examples
+	fi
+}
diff --git a/sci-electronics/iverilog/iverilog-9999.ebuild b/sci-electronics/iverilog/iverilog-9999.ebuild
new file mode 100644
index 000000000000..183ed6f2023f
--- /dev/null
+++ b/sci-electronics/iverilog/iverilog-9999.ebuild
@@ -0,0 +1,68 @@
+# Copyright 1999-2020 Gentoo Authors
+# Distributed under the terms of the GNU General Public License v2
+
+EAPI=7
+
+inherit autotools
+
+GITHUB_PV=$(ver_rs 1- '_')
+
+DESCRIPTION="A Verilog simulation and synthesis tool"
+HOMEPAGE="
+	http://iverilog.icarus.com
+	https://github.com/steveicarus/iverilog
+"
+
+if [[ ${PV} == "9999" ]] ; then
+	inherit git-r3
+	EGIT_REPO_URI="https://github.com/steveicarus/${PN}.git"
+else
+	SRC_URI="https://github.com/steveicarus/${PN}/archive/v${GITHUB_PV}.tar.gz -> ${P}.tar.gz"
+	KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sh ~sparc ~x86"
+	S="${WORKDIR}/${PN}-${GITHUB_PV}"
+fi
+
+LICENSE="LGPL-2.1"
+SLOT="0"
+IUSE="examples"
+
+# If you are building from git, you will also need gperf to generate
+# the configure scripts.
+RDEPEND="
+	sys-libs/readline:0
+	sys-libs/zlib
+"
+
+DEPEND="
+	dev-util/gperf
+	${RDEPEND}
+"
+
+src_prepare() {
+	default
+
+	# From upstreams autoconf.sh, to make it utilize the autotools eclass
+	# Here translate the autoconf.sh, equivalent to the following code
+	# > sh autoconf.sh
+
+	# Autoconf in root ...
+	eautoconf --force
+	# Precompiling lexor_keyword.gperf
+	gperf -o -i 7 -C -k 1-4,6,9,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc || die
+	# Precompiling vhdlpp/lexor_keyword.gperf
+	cd vhdlpp || die
+	gperf -o -i 7 --ignore-case -C -k 1-4,6,9,\$ -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc || die
+}
+
+src_install() {
+	local DOCS=( *.txt )
+	# Default build fails with parallel jobs,
+	# https://github.com/steveicarus/iverilog/pull/294
+	emake installdirs DESTDIR="${D}"
+	default
+
+	if use examples; then
+		dodoc -r examples
+		docompress -x /usr/share/doc/${PF}/examples
+	fi
+}
diff --git a/sci-electronics/iverilog/metadata.xml b/sci-electronics/iverilog/metadata.xml
index 21d969b3bbd1..edc7fde50a36 100644
--- a/sci-electronics/iverilog/metadata.xml
+++ b/sci-electronics/iverilog/metadata.xml
@@ -1,14 +1,25 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd">
 <pkgmetadata>
-  <maintainer type="project">
-    <email>sci-electronics@gentoo.org</email>
-    <name>Gentoo Electronics Project</name>
-  </maintainer>
-  <longdescription>
-  Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
-  compiler, compiling source code writen in Verilog (IEEE-1364) into some target
-  format. The compiler proper is intended to parse and elaborate design
-  descriptions written to the IEEE standard IEEE Std 1364-2001.
-  </longdescription>
+	<maintainer type="person">
+		<email>vowstar@gmail.com</email>
+		<name>Huang Rui</name>
+	</maintainer>
+	<maintainer type="project">
+		<email>sci-electronics@gentoo.org</email>
+		<name>Gentoo Electronics Project</name>
+	</maintainer>
+	<maintainer type="project">
+		<email>proxy-maint@gentoo.org</email>
+		<name>Proxy Maintainers</name>
+	</maintainer>
+	<upstream>
+		<remote-id type="github">steveicarus/iverilog</remote-id>
+	</upstream>
+	<longdescription>
+	Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
+	compiler, compiling source code writen in Verilog (IEEE-1364) into some target
+	format. The compiler proper is intended to parse and elaborate design
+	descriptions written to the IEEE standard IEEE Std 1364-2001.
+	</longdescription>
 </pkgmetadata>